Sun 22 - Fri 27 October 2023 Cascais, Portugal

Weak persistent memory (a.k.a. non-volatile memory) is an emerging technology that offers fast byte-addressable durable main memory.
A wealth of algorithms and libraries has been developed to explore this exciting technology.
As noted by others, this has led to a significant verification gap.
Towards closing this gap, we present Spirea, the first concurrent separation logic for verification of programs under a weak persistent memory model.
Spirea is based on the Iris and Perennial verification frameworks, and by combining features from these logics with novel techniques it supports high-level modular reasoning about crash-safe and thread-safe programs and libraries.
Spirea is fully mechanized in the Coq proof assistant and allows for interactive development of proofs with the Iris Proof Mode.
We use Spirea to verify several challenging examples with modular specifications.
We show how our logic can verify thread-safety and crash-safety of non-blocking durable data structures with null-recovery,
in particular the Treiber stack and the Michael-Scott queue adapted to persistent memory.
This is the first time durable data structures have been verified with a program logic.