Gigue: A JIT Code Binary Generator for Hardware Testing
Just-in-time compilers are the main virtual machine components responsible for performance. They recompile frequently used source code to machine code directly, avoiding the slower interpretation path. Hardware acceleration and performant security primitives would benefit the generated JIT code directly and increase the adoption of hardware-enforced primitives in a high-level execution component.
The RISC-V instruction set architecture presents extension capabilities to design and integrate custom instructions. It is available as open-source and several capable open-source cores coexist, usable for prototyping. Testing JIT-compiler-specific instruction extensions would require extending the JIT compiler itself, other VM components, the underlying operating system, and the hardware implementation itself. As the cost of hardware prototyping is already high, a lightweight representation of the JIT compiler code region in memory would ease prototyping and implementation of new solutions.
In this work, we present Gigue, a binary generator that outputs OS-independent executable JIT code region snapshots. Its main goal is to speed up hardware extension prototyping by keeping it centered around the JIT compiler use case. It is modular and heavily configurable to qualify different JIT code regions implementations from VMs and different running applications. We show how the generated binaries can be extended with three custom extensions, which execution is guaranteed by Gigue’s testing framework. We also present different application case generation and execution on top of a fully-featured RISC-V core.
Mon 23 OctDisplayed time zone: Lisbon change
16:00 - 17:30
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Juan Fumero University of Manchester, György Rethy ETH Zurich, Athanasios Stratikopoulos University of Manchester, Nikos Foutris University of Manchester, Christos Kotselidis University of ManchesterDOI Pre-print
|Gigue: A JIT Code Binary Generator for Hardware Testing
Andrea Rosà USI Lugano