CHERI Performance Enhancement for a Bytecode Interpreter
During our port of the MicroPython bytecode interpreter to the CHERI-based Arm Morello platform, we encountered a number of serious performance degradations. This paper explores several of these of these performance issues in detail, in each case characterizing the cause of the problem, the fix, and the corresponding performance improvement over a set of standard Python benchmarks. While we recognize that Morello is a prototypical physical instantiation of the CHERI concept, we show that it is possible to eliminate certain kinds of software-induced runtime overhead that occur due to the larger size of architectural capabilities relative to native pointers. In our case, we reduce a geometric mean benchmark slowdown from 5x (before optimization) to 2x (after optimization) relative to AArch64 execution. The worst-case slowdowns are greatly improved, from 100x (before optimization) to 2x (after optimization). The key insight is that pointer size assumptions pervade systems code; whereas previous CHERI porting projects highlighted compile-time and execution-time errors exposed by pointer size assumptions, we instead focus on the performance implications of such assumptions.
Mon 23 OctDisplayed time zone: Lisbon change
09:00 - 10:30 | |||
09:00 10mDay opening | Opening Remarks VMIL Andrea Rosà USI Lugano File Attached | ||
09:10 25mPaper | CHERI Performance Enhancement for a Bytecode Interpreter VMIL Duncan Lowther University of Glasgow, Dejice Jacob University of Glasgow, Jeremy Singer University of Glasgow DOI Pre-print | ||
09:35 25mPaper | Revisiting Dynamic Dispatch for Modern Architectures VMIL Dave Mason Toronto Metropolitan University (formerly Ryerson University) | ||
10:00 15mShort-paper | Extraction of Virtual Machine Execution Traces VMIL | ||
10:15 15mShort-paper | Transpiling Slang Methods to C Functions: An Example of Static Polymorphism for Smalltalk VM ObjectsRemote VMIL Tom Braun Hasso Plattner Institute, University of Potsdam, Germany, Marcel Taeumel University of Potsdam; Hasso Plattner Institute, Eliot Miranda Cadence Design Systems, Robert Hirschfeld University of Potsdam; Hasso Plattner Institute DOI Pre-print |